1. Field of the Invention
This invention relates to a method of fabricating a semiconductor integrated circuit device having high density and suitable for high speed operation.
2. Description of the Prior Art
Semiconductor integrated circuits show promise as devices which can provide high density, high speed and low power consumption. However, there is one problem which must be overcome before these advantages can be effectively implemented. It is a parasitic capacitance. Its reduction may permit a higher-speed lower-power-consumption device to be manufactured. Thus, many attempts have been made to reduce parasitic capacitance.
One example is a method whereby monocrystalline insulating substrate, e.g., sapphire is employed to effect vapor growth of silicon thereon. This substrate is normally called a SOS (Silicon On Sapphire).
FIGS. 1a to 1d show the steps employed in carrying out this method. In FIG. 1a, a silicon layer is grown on a sapphire substrate 1 by a vapor growth method and then an n-type impurity is diffused thereinto, which changes the silicon layer into an n.sup.+ layer 2. Next, as shown in FIG. 1b, a silicon oxide film 4 and a silicon nitride film 5 are formed on the area which is to be an island region of the n-type region 3 and thereafter the n-type region 3 is etched in the direction of depth. Then, as shown in FIG. 1c, a selective oxidation is performed using the silicon nitride film 5 as a mask thereby to form a silicon oxide film 6 the bottom of which reaches the sapphire substrate 1, and thereafter the silicon oxide film 4 and silicon nitride 5 are removed. Finally, as shown in FIG. 1d, a base region 7 and emitter region 8 are diffused into the n-type island region 3 which is surrounded by the sapphire substrate 1 at its bottom and by the silicon oxide film 6 at its side, and thereafter an emitter electrode 9, a base electrode 10 and a collector electrode 11 are formed in ohmic contact with the emitter region 8, the base region 7 and the n.sup.+ type layer 2, thereby obtaining an npn bipolar transistor.
The device fabricated by the method described above possesses the excellent feature of low parasitic capacitance which is attributable to the complete separation of the island region by an insulator, but also possesses the following defects:
(1) It is expensive since monocrystalline sapphire is used as a substrate.
(2) A heat treatment at high temperature during the fabrication process of the device evaporates or diffuses alumina (Al.sub.2 O.sub.3) from the sapphire substrate, which contaminates an electric furnace, etc.
Due to these two defects, the above device has not been widely used.
Japanese Patent Application Kokai (Laid-Open) No. 8346/84 specification discloses another method of completely separating a device area by an insulator. In this method, an n.sup.+ buried region below a monocrystalline silicon layer is subjected to anisotropic etching, and then the n.sup.+ type region thus left beneath the monocrystalline silicon layer is oxidized to completely separate the monocrystalline silicon region by the thus formed oxide film. This monocrystalline silicon layer is made of an epitaxial layer which is grown on a monocrystalline silicon substrate having the n.sup.+ buried region on its surface.